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India Wire Cadence CEO is back again to woo Indian chip designers
India Wire Cadence CEO is back again to woo Indian chip designers | Cadence CEO is back again to woo Indian chip designers |
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| Written by Sufia Tippu | |
| Sunday, 15 October 2006 | |
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Page 2 of 2 The three Cs -- computing, consumer, and communications markets -- consume a majority of the semiconductors manufactured, and are estimated to grow with a healthy CAGR through 2009. To date, successful custom design has been resource-intensive and thus, the preserve of a few large companies. Insufficient automation has always been a key challenge. “Our newly launched custom chip design platform, Virtuoso 6.1 enables designers to streamline the processes so that companies can cut costs by eliminating re-spins and commit to volume productions to their OEM customers,” Fister explained. Platform based design is the way forward to address System-on-chip (SoC) design challenges. In this approach, some portion of the chip’s architecture is predefined for a specific type of application, enabling extensive design reuse and therefore providing faster time-to-market (TTM). Companies using a platform based design approach have reported, on an average, 9X productivity gains from the first platform to the derivative products. Companies have seen their TTM for derivatives shrink up to 75 per cent and their time-to-volume shrink up to 50%. In addition, platform based design offers increased flexibility helping companies reach multiple customers and market segments with minor changes to the original platform. “But despite its obvious benefits, platform based design is still a complex process and in order to enable mass adoption of this design technology, EDA technology must evolve,” he added. {moscomment}
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